Power consumption has become an important optimization metric in the design of micro-electronic circuits. Optimizing the power consumption may be achieved at various abstract levels of design, from algorithmic and system levels down to layout and circuit levels. In general, the power consumption of an electronic system may be dependent upon its capacitance, the clock signals, or its power supply voltage.
The need to conserve power consumption within an integrated circuit (“IC”) chip becomes more critical for those IC chips utilized within the Internet of Things (“IoT”), because such IC chips are often required to be portable, ubiquitous, and very small (and thus being powered by small, low power batteries). Additionally, in order to competitively manufacture and market such IC chips to a wide variety of end users, such IC chips need to be robustly designed for use in a wide variety of potential applications.
One possible solution is to design and manufacture an IC chip possessing only the minimal hardware required for performing a particular end user application, which can then be customized so as to minimize its size, needed circuitry, and thus required power for performing the particular set of functions for the dedicated application. Though such an IC chip designed and manufactured with such application dedicated hardware may result in an ideal solution, it is not financially feasible for an IC manufacturer to produce and sell such customized solutions for each different customer.
The prior art has attempted to address the foregoing problems in a couple of different ways. A first solution is to write specialized software code for the end user's application, which activates and deactivates power to various portions of circuitry on an as-needed basis. However, such a solution requires writing of a specific power management code for each application to be run by the IC chip (or for the same application to be run on a different IC chip), which can be very expensive to design, implement, and debug since the specialized software code is not transferable and usable within the IC chip when it is intended for use with other applications. Furthermore, such a complex endeavor is error prone, because it requires a thorough understanding of each application to be run by the IC chip. A second solution is to manage the clock gating within the various portions of the IC in order to deactivate portions of the IC when it is known that those portions of the IC are not going to be effective in that instance. This solution is also not economically feasible because the hardware must be designed to take into account circumstantial internal conditions within the integrated circuit as they arise during the often numerous alternative variations in how portions of the circuitry are utilized over a wide variety of conditions in which the applications may operate. The circuit designer has to thus design the clock gating at the logic level through logic restructuring and operand isolation in order to take into account each of these potential variations.